Contributed by johan on from the cpu's-all-around dept.
Tobias Weingartner (weingart@) asked for more tests in an updated cpuid.c on tech and misc mailing lists. A previous post covered the beginnings of this. Any and all i386 and amd64 cpus are welcome. Of course, really bizarre things would be even better (there's a lot of current Intel/AMD cpus around). Of special interest would be Via Nano, Intel Atom, older cpus or anything with OpenBSD running on a virtual server. Toby would love to have reports (along with uname -a and vm software version used) so he can extend cpuid.c to grok even more vm information.
Please read on for Toby's mail:
List: openbsd-tech Subject: New cpuid code to test From: Tobias WeingartnerDate: 2008-10-19 21:40:59 Hello all, I'd love to get another round of cpuid testing done (i386/amd64). The code is available at: http://www.tepid.org/~weingart/cpuid.c I'd appreciate it if people could do something like the following on their i386 and amd64 boxes: make cpuid && ./cpuid | mail -s 'cpuid output' weingart@tepid.org Thanks, --Toby.
Sample output should look something like this:
Found 686 class CPU with CPUID support. Base: 'GenuineIntel', max cpuid level = 10 Base: Ext Family/Model = 0/0 Base: Family/Model/Step = 6/15/6 Base: Type = 'Original OEM processor' Base: FMS = 0x0060f06 Base: APIC ID = 0 Base: Count = 2 Base: Chunks = 8 Base: BrandID = 0 Base: HTT = 1, LCores = 2, PCores = 2 Base-Feature: FPU, Floating Point Unit On-chip Base-Feature: VME, Virtual Mode Extension Base-Feature: DE, Debugging Extension Base-Feature: PSE, Page Size Extension Base-Feature: TSC, Time-Stamp Counter Base-Feature: MSR, Model Specific Registers Base-Feature: PAE, Physical Address Extension Base-Feature: MCE, Machine Check Exception Base-Feature: CX8, CMPXCHG8 Instruction Supported Base-Feature: APIC, On-chip APIC Hardware Supported Base-Feature: SEP, Fast System Call Base-Feature: MTRR, Memory Type Range Registers Base-Feature: PGE, Page Global Enable Base-Feature: MCA, Machine Check Architecture Base-Feature: CMOV, Conditional Move Instruction Supported Base-Feature: PAT, Page Attribute Table Base-Feature: PSE36, 36-bit Page Size Extension Base-Feature: CLFSH, CLFLUSH Instruction Supported Base-Feature: DS, Debug Store Base-Feature: ACPI, Thermal Monitor & Software Controlled Clock Base-Feature: MMX, IA32 MMX Supported Base-Feature: FXSR, Fast Floating Point Save and Restore Base-Feature: SSE, Streaming SIMD Extensions Supported Base-Feature: SSE2, Steaming SIMD Extensions 2 Supported Base-Feature: SS, Self-Snoop Base-Feature: HTT, Hyper-Threading Supported Base-Feature: TM, Thermal Monitor Supported Base-Feature: PBE, Pending Break Enable Base-Feature: SSE3, Streaming SIMD Extensions 3 Supported Base-Feature: DTES64, 64-bit Debug Store Base-Feature: MONITOR, Monitor/MWait Instructions Supported Base-Feature: DS-CPL, CPL Qualified Debug Store Base-Feature: VMX, Virtual Machine Extensions Base-Feature: EST, Enhanced Intel SpeedStep Base-Feature: TM2, Thermal Monitor 2 Base-Feature: SSSE3, Supplemental Streaming SIMD Extensions 3 Base-Feature: CX16, CMPXCHG16B Instruction Support Base-Feature: xTPR, Send Task Priority Messages Base-Feature: PDCM, Performance Capabilities MSR Base-Cache-Desc: 1 page(s) of cache descriptors Base-Cache-Desc(0x5): 32-entry, 4M page data TLB, 4-way set associative Base-Cache-Desc(0xB0): 128-entry, 4K page instruction TLB, 4-way set associative Base-Cache-Desc(0xB1): 4-entry, 4M page instruction TLB, 4-way set associative Base-Cache-Desc(0x56): 16-entry, 4M page data TLB, 4-way set associative Base-Cache-Desc(0x57): 16-entry, 4K page data TLB, 4-way set associative Base-Cache-Desc(0xF0): 64-byte Prefetch Base-Cache-Desc(0x2C): 32K 8-way, 64-byte line, level 1 data cache Base-Cache-Desc(0xB4): 256-entry, 4K page data TLB, 4-way set associative Base-Cache-Desc(0x30): 32K 8-way, 64-byte line, level 1 instruction cache Base-Cache-Desc(0x49): 4M 16-way, 64-byte line, level 2 unified cache Base-PSN: disabled Base-Cache-Det: nthr=1, full=0, init=1 Base-Cache-Det: ppart=1, sline=64, nset=64, pref=1 Base-Cache-Det: 32KB 8-way 64 byte/line level-1 Data Cache Base-Cache-Det: nthr=1, full=0, init=1 Base-Cache-Det: ppart=1, sline=64, nset=64, pref=1 Base-Cache-Det: 32KB 8-way 64 byte/line level-1 Instruction Cache Base-Cache-Det: nthr=2, full=0, init=1 Base-Cache-Det: ppart=1, sline=64, nset=4096, pref=1 Base-Cache-Det: 4MB 16-way 64 byte/line level-2 Unified Cache Base: CPU = 'Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz' Ext: max vendor cpuid level = 0x80000008 Ext: brand string = 'Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz' 0x00000000: 0x0000000a 0x756e6547 0x6c65746e 0x49656e69 ....GenuntelineI 0x00000001: 0x000006f6 0x00020800 0x0000e3bd 0xbfebfbff ................ 0x00000002: 0x05b0b101 0x005657f0 0x00000000 0x2cb43049 .....WV.....I0., 0x00000003: 0x00000000 0x00000000 0x00000000 0x00000000 ................ 0x00000004: 0x04000121 0x01c0003f 0x0000003f 0x00000001 !...?...?....... 0x00000005: 0x00000040 0x00000040 0x00000003 0x00022220 @...@....... ".. 0x00000006: 0x00000001 0x00000002 0x00000001 0x00000000 ................ 0x00000007: 0x00000000 0x00000000 0x00000000 0x00000000 ................ 0x00000008: 0x00000400 0x00000000 0x00000000 0x00000000 ................ 0x00000009: 0x00000000 0x00000000 0x00000000 0x00000000 ................ 0x0000000a: 0x07280202 0x00000000 0x00000000 0x00000000 ..(............. 0x80000000: 0x80000008 0x00000000 0x00000000 0x00000000 ................ 0x80000001: 0x00000000 0x00000000 0x00000001 0x20100800 ............... 0x80000002: 0x65746e49 0x2952286c 0x726f4320 0x4d542865 Intel(R) Core(TM 0x80000003: 0x43203229 0x20205550 0x20202020 0x54202020 )2 CPU T 0x80000004: 0x30303237 0x20402020 0x30302e32 0x007a4847 7200 @ 2.00GHz. 0x80000005: 0x00000000 0x00000000 0x00000000 0x00000000 ................ 0x80000006: 0x00000000 0x00000000 0x10008040 0x00000000 ........@....... 0x80000007: 0x00000000 0x00000000 0x00000000 0x00000000 ................ 0x80000008: 0x00003024 0x00000000 0x00000000 0x00000000 $0..............
(Comments are closed)
By Anonymous Coward (129.128.4.7) on
A current 'wc -l' style output of the CPU brand string looks like:
The "(Unknown CPU Brand String)" ones are CPUs that don't give us any way of identifying them, other than using heuristics and tables which I've not included in the program yet.Anyways, I've had 130+ downloads of the source, and there's 80+ in the greylisting pipeline. I'd love to get more.
Comments
By Anonymous Coward (219.90.160.197) on
Comments
By Shane J Pearson (203.20.79.230) on
>
> 0x00000000: 0x00000001 0x68747541 0x444d4163 0x69746e65 ....AuthcAMDenti
>
> 0x00000000: 0x0000000a 0x756e6547 0x6c65746e 0x49656e69 ....GenuntelineI
32bit endianess?
By Anonymous Coward (68.148.4.19) on
>
> 0x00000000: 0x00000001 0x68747541 0x444d4163 0x69746e65 ....AuthcAMDenti
>
> 0x00000000: 0x0000000a 0x756e6547 0x6c65746e 0x49656e69 ....GenuntelineI
That's normal.
-Toby.
By Altadel (68.149.160.222) on
> greylisting pipeline. I'd love to get more.
I just sent about 6-8 more, from boxen P133 through Xeon 5148, with a Via Ezra thrown in.
HTH.
By Wouter (2001:888:1b6b:b0e::6965:6b73) on
#include <libkern/i386/_OSByteOrder.h>
#define swap32 _OSSwapInt32
and then compile it with -mdynamic-no-pic. Yes, they're hacks. However, cpuid then compiles without warnings (nice!).
My $old-gen macbook probably isn't very useful (it has a rather pedestrian processor), but maybe somebody can test this program on one of the recently released macs? Those usually have more exotic silicon.
Comments
By tedu (74.66.20.150) on
> My $old-gen macbook probably isn't very useful (it has a rather pedestrian processor), but maybe somebody can test this program on one of the recently released macs? Those usually have more exotic silicon.
If the point of the exercise is to make sure everything still works in the future and only the newest machines get tested, guess what's likely to happen to support for the older machines?
By Anonymous Coward (129.128.4.7) on
Also, I've fixed a few bugs here and there, including one from the new AMD quad core chips (cache descriptors were zero'd). Also, there is a fix in there to fix the "cpu class", down-grading the class if the family happens to be lower than the discovered class. Another fix that I've put in is the extra functions needed to get this to compile on linux and osx. It should largely compile with gcc on most things at this point. (Not sure about cygwin/windows).
I'd love more tests (download a new copy). Pretty good coverage so far. At last count, we have (roughly) things looking like:
That's some roughly 200 distinct CPUs, from 482 CPUs. Decent spread of things out there. Thank you to all the people that managed to get those old and very weird machines running.
-Toby.
Comments
By Anonymous Coward (217.31.65.40) on
Just statistics?
Comments
By Anonymous Coward (129.128.4.7) on
>
> Just statistics?
Nope, this is to make code that handles cpu identification in
a different way.
-Toby.
PS: Yes, they could be jokes, but then so can every bug report out
there, right? In the end you get what you return. Return a joke
for a report, and you get a joke of a software in return.
By Anonymous Coward (87.178.158.90) on
> of things out there. Thank you to all the people that managed to get
> those old and very weird machines running.
Did you consider that there might be fakes (jokes, whatnots)?
They might even evolve into a security risk if relied upon in scripts people make.
Comments
By tedu (udet) on
> > of things out there. Thank you to all the people that managed to get
> > those old and very weird machines running.
>
> Did you consider that there might be fakes (jokes, whatnots)?
>
> They might even evolve into a security risk if relied upon in scripts people make.
>
please explain.
By Anonymous Coward (87.178.158.90) on
Linguistical typo forensics tell me the writer of this text is probably a German.
Comments
By Anonymous Coward (129.128.4.7) on
>
> Linguistical typo forensics tell me the writer of this text is probably a German.
Tester must be an italian... (fast). That version was only up
for a short time... :)
-Toby.
By Anonymous Coward (129.128.4.7) on
If you have a cpu not on this list, I'd love to get the output from cpuid from you. If you have cpus that show up as 'Unknown', then a re-run of a newer cpuid version (I've added a version number to the first line it prints) would be appreciated. Since the original post, cpuid.c has gone through at least a dozen revisions.
-Toby.
Comments
By Brynet (Brynet) on
> 1 Base: CPU = 'OASIS Vcpu'
> ...
>
> -Toby.
>
Hey, a little off topic.. sorta.. but what is this? :)
Comments
By Colin D. (cdidier) on http://cybione.org/
> > 1 Base: CPU = 'OASIS Vcpu'
> > ...
> >
> > -Toby.
> >
>
> Hey, a little off topic.. sorta.. but what is this? :)
It's the name of a CPU seen by a virtual machine running as a KVM guest, from the hoster lost-oasis.fr.